3.3V 2M x 8/1M x 16 CMOS synchronous DRAM

Functional description The AS4LC2M8S1 and AS4LC1M16S1 are high-performance 16-megabit CMOS Synchronous Dynamic Random Access Memory (SDRAM) devices organized as 1,048,576 words × 8 bits × 2 banks (2048 rows × 512 columns) and 524,288 words × 16 bits × 2 banks (2048 rows × 256 columns), respective

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3.3V 256K X 16 CMOS DRAM (EDO)

Functional description The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely

文件：530.56 Kbytes 页数：25 Pages

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3.3V 256K X 16 CMOS DRAM (EDO)

Functional description The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely

文件：530.56 Kbytes 页数：25 Pages

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3.3V 256K X 16 CMOS DRAM (EDO)

Functional description The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely

文件：530.56 Kbytes 页数：25 Pages

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3.3V 256K X 16 CMOS DRAM (EDO)

Functional description The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely

文件：530.56 Kbytes 页数：25 Pages

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3.3V 256K X 16 CMOS DRAM (EDO)

Functional description The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely

文件：530.56 Kbytes 页数：25 Pages

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3.3V 256K X 16 CMOS DRAM (EDO)

Functional description The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely

文件：530.56 Kbytes 页数：25 Pages

ALSC

3.3V 256K X 16 CMOS DRAM (EDO)

Functional description The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely

文件：530.56 Kbytes 页数：25 Pages

ALSC

3.3V 256K X 16 CMOS DRAM (EDO)

Functional description The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely

文件：530.56 Kbytes 页数：25 Pages

ALSC

3.3V 2M 횞 8/1M 횞 16 CMOS synchronous DRAM

Features • Organization - 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address • All signals referenced to positive edge of clock, fully synchronous • Dual internal banks controlled by A11 (bank sel

文件：721.21 Kbytes 页数：29 Pages

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