AS4LC256K16E0-35JC中文资料ALSC数据手册PDF规格书

Functional description

The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels.

特性 Features

• Organization: 262,144 words × 16 bits

• High speed

- 45/60 ns RAS access time

- 10/12/15/20 ns column address access time

- 7/10/10 ns CAS access time

• Low power consumption

- Active: 280 mW max (AS4LC256K16EO-35)

- Standby: 2.8 mW max, CMOS I/O (AS4LC256K16EO-35)

• EDO page mode

• 5V I/O tolerant

• 512 refresh cycles, 8 ms refresh interval

- RAS-only or CAS-before-RAS refresh or self refresh

• Read-modify-write

• LVTTL-compatible, three-state I/O

• JEDEC standard packages

- 400 mil, 40-pin SOJ

- 400 mil, 40/44-pin TSOP II

• 3.3V power supply

• Latch-up current > 200 mA