丝印：873；Package：16Ld2.6x1.8UTQFN；Buck PWM Controller with Internal Compensation and External Reference Tracking

文件：835.24 Kbytes 页数：17 Pages

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丝印：87321AIL；Package：SOIC；÷1, ÷2 Differential-TO-LVPECL Clock Generator

FEATURES • One differential LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 700MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels

文件：521.919 Kbytes 页数：19 Pages

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丝印：87321AIL；Package：SOIC；÷1, ÷2 Differential-TO-LVPECL Clock Generator

FEATURES • One differential LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 700MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels

文件：521.919 Kbytes 页数：19 Pages

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丝印：87354AIL；Package：SOIC；÷4/÷5 Differential-to-3.3V LVPECL Clock Generator

FEATURES • One differential 3.3V LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL lev

文件：359.17 Kbytes 页数：16 Pages

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丝印：87354AIL；Package：SOIC；÷4/÷5 Differential-to-3.3V LVPECL Clock Generator

FEATURES • One differential 3.3V LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL lev

文件：359.17 Kbytes 页数：16 Pages

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丝印：8735BMI-21LF；Package：SOIC；700MHz, Differential-to-3.3V LVPECL Zero Delay Clock Generator

Features •One differential 3.3V LVPECL output pair, one differential feedback output pair •Differential CLK, nCLK input pair •CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, HCSL •Output frequency range: 31.25MHz to 700MHz •Input frequency range: 31.25

文件：635.27 Kbytes 页数：19 Pages

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丝印：8735BMI-21LF；Package：SOIC；700MHz, Differential-to-3.3V LVPECL Zero Delay Clock Generator

Features •One differential 3.3V LVPECL output pair, one differential feedback output pair •Differential CLK, nCLK input pair •CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, HCSL •Output frequency range: 31.25MHz to 700MHz •Input frequency range: 31.25

文件：635.27 Kbytes 页数：19 Pages

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丝印：873AI；Package：VFQFN；Differential-to-LVDS Buffer/Divider with Internal Termination

Features • Three LVDS outputs • Frequency divide select options: ÷2, ÷4, ÷8, ÷16 • IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML • Output frequency: 2GHz (maximum) in pass-through mode • Additive phase jitter: 0.185ps (typical) RMS • Output skew: 9ps (t

文件：569.65 Kbytes 页数：16 Pages

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丝印：873AI；Package：VFQFN；Differential-to-LVDS Buffer/Divider with Internal Termination

Features • Three LVDS outputs • Frequency divide select options: ÷2, ÷4, ÷8, ÷16 • IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML • Output frequency: 2GHz (maximum) in pass-through mode • Additive phase jitter: 0.185ps (typical) RMS • Output skew: 9ps (t

文件：569.65 Kbytes 页数：16 Pages

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丝印：87312E；Package：VSON；Dual 30-V N-Channel NexFET™ Power MOSFETs

1FEATURES • Common Source Connection • Ultra Low Drain to Drain On-Resistance • Space Saving SON 3.3 x 3.3mm Plastic Package • Optimized for 5V Gate Drive • Low Thermal Resistance • Avalanche Rated • Pb Free Terminal Plating • RoHS Compliant • Halogen Free APPLICATIONS • Adaptor/USB

文件：536.83 Kbytes 页数：15 Pages

TI2

德州仪器