丝印：8735BMI-21LF；Package：SOIC；700MHz, Differential-to-3.3V LVPECL Zero Delay Clock Generator

Features •One differential 3.3V LVPECL output pair, one differential feedback output pair •Differential CLK, nCLK input pair •CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, HCSL •Output frequency range: 31.25MHz to 700MHz •Input frequency range: 31.25

文件：635.27 Kbytes 页数：19 Pages

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瑞萨

丝印：8735BMI-21LF；Package：SOIC；700MHz, Differential-to-3.3V LVPECL Zero Delay Clock Generator

Features •One differential 3.3V LVPECL output pair, one differential feedback output pair •Differential CLK, nCLK input pair •CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, HCSL •Output frequency range: 31.25MHz to 700MHz •Input frequency range: 31.25

文件：635.27 Kbytes 页数：19 Pages

RENESAS

瑞萨

丝印：8735BMI-21LF；Package：SOIC；700MHz, Differential-to-3.3V LVPECL Zero Delay Clock Generator

Features •One differential 3.3V LVPECL output pair, one differential feedback output pair •Differential CLK, nCLK input pair •CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, HCSL •Output frequency range: 31.25MHz to 700MHz •Input frequency range: 31.25

文件：635.27 Kbytes 页数：19 Pages

RENESAS

瑞萨

丝印：8735BMI-21LF；Package：SOIC；700MHz, Differential-to-3.3V LVPECL Zero Delay Clock Generator

Features •One differential 3.3V LVPECL output pair, one differential feedback output pair •Differential CLK, nCLK input pair •CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, HCSL •Output frequency range: 31.25MHz to 700MHz •Input frequency range: 31.25

文件：635.27 Kbytes 页数：19 Pages

RENESAS

瑞萨