8735BMI-21LF集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

特性 Features

•One differential 3.3V LVPECL output pair, one differential feedback output pair

•Differential CLK, nCLK input pair

•CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, HCSL

•Output frequency range: 31.25MHz to 700MHz

•Input frequency range: 31.25MHz to 700MHz

•VCO range: 250MHz to 700MHz

•Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

•External feedback for “zero delay” clock regeneration with configurable frequencies

•Cycle-to-cycle jitter: 50ps (maximum)

•3.3V supply voltage

•-40°C to 85°C ambient operating temperature

•Available in RoHS compliant package