74HC107PW

Dual JK flip-flop with reset; negative-edge trigger

1.Generaldescription The74HC107;74HCT107isadualnegativeedgetriggeredJKflip-flopfeaturingindividualJand Kinputs,clock(CP)andreset(R)inputsandcomplementaryQandQoutputs.Theresetisan asynchronousactiveLOWinputandoperatesindependentlyoftheclockinput.TheJ

74HC107PW-Q100

Dual JK flip-flop with reset; negative-edge trigger

1.Generaldescription The74HC107-Q100;74HCT107-Q100isadualnegativeedgetriggeredJKflip-flopfeaturing individualJandKinputs,clock(CP)andreset(R)inputsandcomplementaryQandQoutputs. TheresetisanasynchronousactiveLOWinputandoperatesindependentlyoftheclockinp

74HC107-Q100

Dual JK flip-flop with reset; negative-edge trigger

1.Generaldescription The74HC107-Q100;74HCT107-Q100isadualnegativeedgetriggeredJKflip-flopfeaturing individualJandKinputs,clock(CP)andreset(R)inputsandcomplementaryQandQoutputs. TheresetisanasynchronousactiveLOWinputandoperatesindependentlyoftheclockinp

74HC109

Dual JK flip-flop with set and reset; positive-edge trigger

GENERALDESCRIPTION The74HC/HCT109arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT109aredualpositive-edgetriggered,JKflip-flopswithindividualJ,Kinputs,clock(CP)

74HC109

Dual JK flip-flop with set and reset; positive-edge-trigger

1.Generaldescription The74HC109;74HCT109isadualpositiveedgetriggeredJKflip-flopfeaturingindividualJand Kinputs,clock(CP)inputs,set(SD)andreset(RD)inputsandcomplementaryQandQoutputs. ThesetandresetareasynchronousactiveLOWinputsandoperateindependentlyof

74HC109

High Speed CMOS Logic

Features OutputDriveCapability:10LSTTLLoads LowInputCurrent:1μA OutputsdirectlyinterfaceCMOS,NMOSandTTL OperatingVoltageRange:2Vto6V CMOSHighNoiseImmunity Functioncompatiblewith74LS109.

74HC109_V01

High Speed CMOS Logic

Features OutputDriveCapability:10LSTTLLoads LowInputCurrent:1μA OutputsdirectlyinterfaceCMOS,NMOSandTTL OperatingVoltageRange:2Vto6V CMOSHighNoiseImmunity Functioncompatiblewith74LS109.

74HC109D

Dual JK flip-flop with set and reset; positive-edge trigger

GENERALDESCRIPTION The74HC/HCT109arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT109aredualpositive-edgetriggered,JKflip-flopswithindividualJ,Kinputs,clock(CP)

74HC109D

Dual JK flip-flop with set and reset; positive-edge-trigger

1.Generaldescription The74HC109;74HCT109isadualpositiveedgetriggeredJKflip-flopfeaturingindividualJand Kinputs,clock(CP)inputs,set(SD)andreset(RD)inputsandcomplementaryQandQoutputs. ThesetandresetareasynchronousactiveLOWinputsandoperateindependentlyof

74HC109DB

Dual JK flip-flop with set and reset; positive-edge trigger

GENERALDESCRIPTION The74HC/HCT109arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT109aredualpositive-edgetriggered,JKflip-flopswithindividualJ,Kinputs,clock(CP)