1. General description

The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and

K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an

asynchronous active LOW input and operates independently of the clock input. The J and K inputs

control the state changes of the flip-flops as described in the mode select function table. The J and

K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable

operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface

inputs to voltages in excess of VCC.

2. Features and benefits

• Wide supply voltage range from 2.0 V to 6.0 V

• CMOS low power dissipation

• High noise immunity

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Complies with JEDEC standards:

• JESD8C (2.7 V to 3.6 V)

• JESD7A (2.0 V to 6.0 V)

• Input levels:

• The 74HC107: CMOS levels

• The 74HCT107: TTL levels

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74HC107PW属于集成电路（IC） > 触发器。安世半导体(中国)有限公司制造生产的74HC107PW触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。