Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp

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Dual JK flip-flop with reset; negative-edge trigger

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Dual JK flip-flop with reset; negative-edge trigger

The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip‑flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs contr • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Input levels:• For 74HC107-Q100: CMOS level\n• For 74HCT107-Q100: TTL level\n\n• Complies with JEDEC standard no. 7A\n• ESD protection:• MIL-STD-883, method 3015 exce;

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Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 14TSSOP

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