74HC107PW-Q100集成电路（IC）的触发器规格书PDF中文资料

厂商型号	74HC107PW-Q100
参数属性	74HC107PW-Q100 封装/外壳为14-TSSOP（0.173"，4.40mm 宽）；包装为卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带；类别为集成电路（IC）的触发器；产品描述：IC FF JK TYPE DUAL 1BIT 14TSSOP
功能描述	Dual JK flip-flop with reset; negative-edge trigger
封装外壳	14-TSSOP（0.173"，4.40mm 宽）
文件大小	259.39 Kbytes
页面数量	15 页
生产厂商	Nexperia B.V. All rights reserved
企业简称	NEXPERIA【安世】
中文名称	安世半导体(中国)有限公司官网
原厂标识
数据手册	下载地址一下载地址二到原厂下载
更新时间	2025-8-3 23:00:00
人工找货	74HC107PW-Q100价格和库存，欢迎联系客服免费人工找货

1. General description

The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring

individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs.

The reset is an asynchronous active LOW input and operates independently of the clock input.

The J and K inputs control the state changes of the flip-flops as described in the mode select

function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock

transition for predictable operation. Inputs include clamp diodes that enable the use of current

limiting resistors to interface inputs to voltages in excess of VCC.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

• Wide supply voltage range from 2.0 V to 6.0 V

• CMOS low power dissipation

• High noise immunity

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Complies with JEDEC standards:

• JESD8C (2.7 V to 3.6 V)

• JESD7A (2.0 V to 6.0 V)

• Input levels:

• For 74HC107-Q100: CMOS level

• For 74HCT107-Q100: TTL level

• ESD protection:

• MIL-STD-883, method 3015 exceeds 2000 V

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)