| 型号 | 下载 订购 | 功能描述 | 制造商 上传企业 | LOGO |
|---|---|---|---|---|
74HC10 | Triple 3-input NAND gate GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. FEATURES • Output capability: standard • ICC categ 文件：34.29 Kbytes 页数：5 Pages | PHI 飞利浦 | PHI | |
74HC10 | Triple 3-input NAND gate 1. General description The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Complies with JEDEC standard JESD7A • Input levels: • For74HC10 文件：224.64 Kbytes 页数：11 Pages | NEXPERIA 安世 | NEXPERIA | |
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc 文件：53.67 Kbytes 页数：7 Pages | PHI 飞利浦 | PHI | ||
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J 文件：259.73 Kbytes 页数：15 Pages | NEXPERIA 安世 | NEXPERIA | ||
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J 文件：259.73 Kbytes 页数：15 Pages | NEXPERIA 安世 | NEXPERIA | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc 文件：53.67 Kbytes 页数：7 Pages | PHI 飞利浦 | PHI | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc 文件：53.67 Kbytes 页数：7 Pages | PHI 飞利浦 | PHI | ||
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp 文件：259.39 Kbytes 页数：15 Pages | NEXPERIA 安世 | NEXPERIA | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc 文件：53.67 Kbytes 页数：7 Pages | PHI 飞利浦 | PHI | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc 文件：53.67 Kbytes 页数：7 Pages | PHI 飞利浦 | PHI |
技术参数
- VCC (V)：
2.0 - 6.0
- Logic switching levels：
CMOS
- Output drive capability (mA)：
± 5.2
- tpd (ns)：
16
- fmax (MHz)：
78
- Power dissipation considerations：
low
- Tamb (°C)：
-40~125
- Rth(j-a) (K/W)：
87
- Ψth(j-top) (K/W)：
6.5
- Rth(j-c) (K/W)：
45
- Package name：
SO14
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
24+ |
DIPSOP |
6000 |
美国德州仪器TEXASINSTRUMENTS原厂代理辉华拓展内地现 |
询价 | |||
2015+ |
5000 |
公司现货库存 |
询价 | ||||
TMS |
06+ |
SOIC |
1000 |
全新原装 绝对有货 |
询价 | ||
HAR |
24+ |
SOP |
988 |
询价 | |||
HIT |
24+ |
N/A |
25843 |
公司原厂原装现货假一罚十!特价出售!强势库存! |
询价 | ||
MOT |
93+ |
SOIC-14/3.9mm |
4 |
原装现货海量库存欢迎咨询 |
询价 | ||
ST |
25+ |
SOP-14 |
2987 |
只售原装自家现货!诚信经营!欢迎来电! |
询价 | ||
Nexperia |
24+ |
SOP |
20000 |
一级代理进口原装现货假一赔十 |
询价 | ||
SGS |
23+ |
SMD-SO14 |
9856 |
原装正品,假一罚百! |
询价 | ||
M |
24+ |
SOP14 |
20000 |
全新原厂原装，进口正品现货，正规渠道可含税！！ |
询价 |
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