74HC107技术资料参数行情报价飞利浦Philips-114ic电子网

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型号	下载订购	功能描述	制造商上传企业	LOGO
74HC107	文件：53.67 Kbytes Page：7 Pages	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc 文件：53.67 Kbytes 页数：7 Pages	PHI 飞利浦	PHI
74HC107	文件：259.73 Kbytes Page：15 Pages	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J 文件：259.73 Kbytes 页数：15 Pages	NEXPERIA 安世	NEXPERIA
74HC107D	文件：259.73 Kbytes Page：15 Pages	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J 文件：259.73 Kbytes 页数：15 Pages	NEXPERIA 安世	NEXPERIA
74HC107D	文件：53.67 Kbytes Page：7 Pages	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc 文件：53.67 Kbytes 页数：7 Pages	PHI 飞利浦	PHI
74HC107DB	文件：53.67 Kbytes Page：7 Pages	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc 文件：53.67 Kbytes 页数：7 Pages	PHI 飞利浦	PHI
74HC107D-Q100	文件：259.39 Kbytes Page：15 Pages	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp 文件：259.39 Kbytes 页数：15 Pages	NEXPERIA 安世	NEXPERIA
74HC107N	文件：53.67 Kbytes Page：7 Pages	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc 文件：53.67 Kbytes 页数：7 Pages	PHI 飞利浦	PHI
74HC107PW	文件：259.73 Kbytes Page：15 Pages	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J 文件：259.73 Kbytes 页数：15 Pages	NEXPERIA 安世	NEXPERIA
74HC107PW	文件：53.67 Kbytes Page：7 Pages	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc 文件：53.67 Kbytes 页数：7 Pages	PHI 飞利浦	PHI
74HC107PW-Q100	文件：259.39 Kbytes Page：15 Pages	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp 文件：259.39 Kbytes 页数：15 Pages	NEXPERIA 安世	NEXPERIA

技术参数

VCC (V)：
2.0 - 6.0
Logic switching levels：
CMOS
Output drive capability (mA)：
± 5.2
tpd (ns)：
16
fmax (MHz)：
78
Power dissipation considerations：
low
Tamb (°C)：
-40~125
Rth(j-a) (K/W)：
87
Ψth(j-top) (K/W)：
6.5
Rth(j-c) (K/W)：
45
Package name：
SO14

供应商	型号	品牌	批号	封装	库存	备注	价格
深圳市一线半导体有限公司	74HC107		24+		111		询价
深圳市福安瓯科技有限公司	74HC107	PHI	25+	TSSOP14	2974	⊙⊙新加坡大量现货库存,深圳常备现货!欢迎查询!⊙	询价
深圳市勤思达科技有限公司	74HC107	恩XP	1215+	SOP	150000	全新原装,绝对正品,公司大量现货供应.	询价
深圳市豪迈兴电子有限公司	74HC107	PHI	24+	TSSOP14	25843	公司原厂原装现货假一罚十!特价出售!强势库存!	询价
上海专毅电子科技有限公司	74HC107	PHI	17+	SOP	9800	原装现货QQ:547425301手机17621633780杨小姐	询价
千层芯半导体(深圳)有限公司	74HC107	Nexperia	24+	SO-14	50000	一级代理进口原装现货假一赔十	询价
深圳市华斯顿科技有限公司	74HC107	MOT	25+23+	SMD	41051	绝对原装正品全新进口深圳现货	询价
深圳市华睿芯科技有限公司	74HC107	M	24+	SOP14	20000	全新原厂原装，进口正品现货，正规渠道可含税！！	询价
深圳市亿智腾科技有限公司	74HC107	PHI	24+	TSSOP14	6540	原装现货/欢迎来电咨询	询价
瀚佳科技(深圳)有限公司	74HC107	MOT	24+	SMD	35200	一级代理分销/放心采购	询价

更多74HC107供应商更新时间2025-11-30 16:30:00

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