Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp

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Dual JK flip-flop with reset; negative-edge trigger

文件：747.99 Kbytes 页数：17 Pages

NEXPERIA

安世

Dual JK flip-flop with reset; negative-edge trigger

文件：747.99 Kbytes 页数：17 Pages

NEXPERIA

安世

Dual JK flip-flop with reset; negative-edge trigger

文件：747.99 Kbytes 页数：17 Pages

NEXPERIA

安世

Dual JK flip-flop with reset; negative-edge trigger

The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the sta • Complies with JEDEC standard no. 7A\n• Input levels:• The 74HC107: CMOS levels\n• The 74HCT107: TTL levels\n\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• Specified from -40 °C to +85 °C and from -40 °C to +125 °C;

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Dual JK flip-flop with reset; negative-edge trigger

The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip‑flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs contr • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Input levels:• For 74HC107-Q100: CMOS level\n• For 74HCT107-Q100: TTL level\n\n• Complies with JEDEC standard no. 7A\n• ESD protection:• MIL-STD-883, method 3015 exce;

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Dual JK flip-flop with reset; negative-edge trigger

The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the sta • Complies with JEDEC standard no. 7A\n• Input levels:• The 74HC107: CMOS levels\n• The 74HCT107: TTL levels\n\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• Specified from -40 °C to +85 °C and from -40 °C to +125 °C;

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Package：14-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 14SO

Nexperia USA Inc.

Package：14-SSOP（0.209"，5.30mm 宽）；包装：卷带（TR） 功能：复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 14SSOP

Nexperia USA Inc.

Package：14-SSOP（0.209"，5.30mm 宽）；包装：卷带（TR） 功能：复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 14SSOP

Nexperia USA Inc.