74HC107D-Q100中文资料Dual JK flip-flop with reset; negative-edge trigger数据手册Nexperia规格书

描述 Description

The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip‑flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip‑flops as described in the mode select function table. The J and K inputs must be stable one set‑up time prior to the HIGH‑to‑LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade1) and is suitable for use in automotive applications.

特性 Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40°C to +85°C and from -40°C to +125°C

• Input levels:
• For 74HC107-Q100: CMOS level
• For 74HCT107-Q100: TTL level

• Complies with JEDEC standard no. 7A
• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0Ω)

• Multiple package options