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74HC107-Q100中文资料PDF规格书
74HC107-Q100规格书详情
1. General description
The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring
individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs.
The reset is an asynchronous active LOW input and operates independently of the clock input.
The J and K inputs control the state changes of the flip-flops as described in the mode select
function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock
transition for predictable operation. Inputs include clamp diodes that enable the use of current
limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Wide supply voltage range from 2.0 V to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Complies with JEDEC standards:
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• Input levels:
• For 74HC107-Q100: CMOS level
• For 74HCT107-Q100: TTL level
• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
TOS |
SOP |
15620 |
一级代理 原装正品假一罚十价格优势长期供货 |
询价 | |||
SGS |
23+ |
SOP3.9 |
90000 |
只做原厂渠道价格优势可提供技术支持 |
询价 | ||
HARRIS/哈里斯 |
21+ |
65200 |
询价 | ||||
MATS |
23+ |
NA |
9856 |
原装正品,假一罚百! |
询价 | ||
SGS |
SOP3.9 |
17432 |
提供BOM表配单只做原装货值得信赖 |
询价 | |||
HAR |
23+ |
sop |
3200 |
全新原装、诚信经营、公司现货销售 |
询价 | ||
SGS |
SOP3.9 |
198589 |
假一罚十原包原标签常备现货! |
询价 | |||
SGS |
98+ |
SOP3.9 |
4485 |
原装现货!低价支持实单!贵了给接受价格! |
询价 | ||
5000 |
公司存货 |
询价 | |||||
TI.PHILIPS |
23+ |
SOP |
25000 |
现货库存,全新原装,特价销售 |
询价 |