3.3 V Communications Clock PLL

Description The MK2049-34 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-34 generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation of clocks freq

文件：135.66 Kbytes 页数：11 Pages

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3.3 V Communications Clock PLL

Description The MK2049-34 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-34 generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation of clocks freq

文件：135.66 Kbytes 页数：11 Pages

ICST

丝印：MK2049-34SI；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL

Features • Packaged in 20-pin SOIC • 3.3 V + 5 operation • Fixed I/O phase relationship on all selections • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8

文件：256.38 Kbytes 页数：10 Pages

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3.3 V Communications Clock PLL

Description The MK2049-35 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-35 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation o

文件：125.68 Kbytes 页数：10 Pages

ICST

3.3 V Communications Clock PLL

Description The MK2049-35 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-35 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation o

文件：125.68 Kbytes 页数：10 Pages

ICST

3.3 V Communications Clock PLL

Description The MK2049-35 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-35 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation o

文件：125.68 Kbytes 页数：10 Pages

ICST

3.3 V Communications Clock PLL

Description The MK2049-36 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation o

文件：125.94 Kbytes 页数：10 Pages

ICST

3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • Pb (lead) free package • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock or

文件：248.79 Kbytes 页数：9 Pages

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3.3 V Communications Clock PLL

Description The MK2049-36 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation o

文件：125.94 Kbytes 页数：10 Pages

ICST

丝印：MK2049-36SILF；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • Pb (lead) free package • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock or

文件：248.79 Kbytes 页数：9 Pages

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