丝印：MK2049-45SILF；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to

文件：410.92 Kbytes 页数：11 Pages

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丝印：MK2049-45SILF；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to

文件：410.92 Kbytes 页数：11 Pages

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瑞萨

3.3V Communications Clock PLL

Description The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication.

文件：182.72 Kbytes 页数：9 Pages

ICST

丝印：MK2049-45SI；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to

文件：410.92 Kbytes 页数：11 Pages

RENESAS

瑞萨

3.3V Communications Clock PLL

Description The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication.

文件：182.72 Kbytes 页数：9 Pages

ICST

Communications Clock Jitter Attenuator

Description The MK2058-01 is a VCXO (Voltage Controlled Crystal Oscillator) based clock jitter attenuator designed for system clock distribution applications. This monolithic IC, combined with an external inexpensive quartz crystal, can be used to replace a more costly hybrid VCXO retiming module

文件：150.08 Kbytes 页数：10 Pages

ICST

COMMUNICATIONS CLOCK JITTER ATTENUATOR

Features • Excellent jitter attenuation for telecom clocks • Also serves as a general purpose clock jitter attenuator for distributed system clocks and recovered data or video clocks • 2:1 Input MUX for input reference clocks • No switching glitches on output • VCXO-based clock generation o

文件：413.81 Kbytes 页数：12 Pages

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瑞萨

Communications Clock Jitter Attenuator

Description The MK2058-01 is a VCXO (Voltage Controlled Crystal Oscillator) based clock jitter attenuator designed for system clock distribution applications. This monolithic IC, combined with an external inexpensive quartz crystal, can be used to replace a more costly hybrid VCXO retiming module

文件：150.08 Kbytes 页数：10 Pages

ICST

丝印：MK2058-01SILF；Package：SOIC；COMMUNICATIONS CLOCK JITTER ATTENUATOR

Features • Excellent jitter attenuation for telecom clocks • Also serves as a general purpose clock jitter attenuator for distributed system clocks and recovered data or video clocks • 2:1 Input MUX for input reference clocks • No switching glitches on output • VCXO-based clock generation o

文件：413.81 Kbytes 页数：12 Pages

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瑞萨

丝印：MK2058-01SILF；Package：SOIC；COMMUNICATIONS CLOCK JITTER ATTENUATOR

Features • Excellent jitter attenuation for telecom clocks • Also serves as a general purpose clock jitter attenuator for distributed system clocks and recovered data or video clocks • 2:1 Input MUX for input reference clocks • No switching glitches on output • VCXO-based clock generation o

文件：413.81 Kbytes 页数：12 Pages

RENESAS

瑞萨