General-purpose Relays and Power Relays Sockets

文件：878.49 Kbytes 页数：27 Pages

OMRON

欧姆龙

丝印：MK2049-34SI；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL

Features • Packaged in 20-pin SOIC • 3.3 V + 5 operation • Fixed I/O phase relationship on all selections • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8

文件：256.38 Kbytes 页数：10 Pages

RENESAS

瑞萨

丝印：MK2049-34SI；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL

Features • Packaged in 20-pin SOIC • 3.3 V + 5 operation • Fixed I/O phase relationship on all selections • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8

文件：256.38 Kbytes 页数：10 Pages

RENESAS

瑞萨

丝印：MK2049-36SILF；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • Pb (lead) free package • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock or

文件：248.79 Kbytes 页数：9 Pages

RENESAS

瑞萨

丝印：MK2049-36SILF；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • Pb (lead) free package • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock or

文件：248.79 Kbytes 页数：9 Pages

RENESAS

瑞萨

丝印：MK2049-45SI；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to

文件：410.92 Kbytes 页数：11 Pages

RENESAS

瑞萨

丝印：MK2049-45SILF；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to

文件：410.92 Kbytes 页数：11 Pages

RENESAS

瑞萨

丝印：MK2049-45SILF；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to

文件：410.92 Kbytes 页数：11 Pages

RENESAS

瑞萨

丝印：MK2049-45SI；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to

文件：410.92 Kbytes 页数：11 Pages

RENESAS

瑞萨

丝印：MK2058-01SILF；Package：SOIC；COMMUNICATIONS CLOCK JITTER ATTENUATOR

Features • Excellent jitter attenuation for telecom clocks • Also serves as a general purpose clock jitter attenuator for distributed system clocks and recovered data or video clocks • 2:1 Input MUX for input reference clocks • No switching glitches on output • VCXO-based clock generation o

文件：413.81 Kbytes 页数：12 Pages

RENESAS

瑞萨