MK2049-36

3.3 V Communications Clock PLL

Description TheMK2049-36isaPhase-LockedLoop(PLL)basedclocksynthesizerthatacceptsmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-36generatesT1,E1,T3,E3,OC3/3,GigabitEthernet,andothercommunicationsfrequencies.Thisallowsforthegenerationo

MK2049-36

3.3 VOLT COMMUNICATIONS CLOCK PLL

Features •Packagedin20pinSOIC •Pb(lead)freepackage •3.3V+5operation •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8kHzbackplaneclockor

MK2049-36

3.3V Communications Clock PLL

The MK2049-36 is a Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications frequencies. This allows for the generation of clocks frequency-locked to an 8 k; Packaged in 20 pin SOIC\nPb (lead) free package\n3.3 V + 5% operation\nMeets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E\nAccepts multiple inputs: 8 kHz backplane clock or 10 to 50 MHz\nLocks;

MK2049-36SI

3.3 V Communications Clock PLL

Description TheMK2049-36isaPhase-LockedLoop(PLL)basedclocksynthesizerthatacceptsmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-36generatesT1,E1,T3,E3,OC3/3,GigabitEthernet,andothercommunicationsfrequencies.Thisallowsforthegenerationo

MK2049-36SILF

丝印：MK2049-36SILF；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features •Packagedin20pinSOIC •Pb(lead)freepackage •3.3V+5operation •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8kHzbackplaneclockor

MK2049-36SILFTR

丝印：MK2049-36SILF；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features •Packagedin20pinSOIC •Pb(lead)freepackage •3.3V+5operation •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8kHzbackplaneclockor

MK2049-36SITR

3.3 V Communications Clock PLL

Description TheMK2049-36isaPhase-LockedLoop(PLL)basedclocksynthesizerthatacceptsmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-36generatesT1,E1,T3,E3,OC3/3,GigabitEthernet,andothercommunicationsfrequencies.Thisallowsforthegenerationo

MK2049-36SILF

Package：20-SOIC（0.295"，7.50mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC VCXO PLL CLK SYNTH 20-SOIC

Renesas Electronics America Inc

MK2049-36SILFTR

Package：20-SOIC（0.295"，7.50mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC VCXO PLL CLK SYNTH 20-SOIC

Renesas Electronics America Inc

MK2049-36SITR

Package：20-SOIC（0.295"，7.50mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC VCXO PLL CLK SYNTH 20-SOIC

Renesas Electronics America Inc