ZL30117数据手册集成电路（IC）的应用特定时钟/定时规格书PDF

描述 Description

The ZL30117 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. The DPLL is capable of locking to one of three input references and provides a wide variety of synchronized output clocks and frame pulses.

特性 Features

Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813
Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64
Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz
Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz
Supports automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth
Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency
Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities

简介

ZL30117属于集成电路（IC）的应用特定时钟/定时。由制造生产的ZL30117应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。