ZL30101中文资料PDH System Synchronizer数据手册Microchip规格书

描述 Description

The ZL30101 Stratum 3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment.The ZL30101 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.The ZL30101 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.

特性 Features

Supports Telcordia GR-1244-CORE Stratum 3
Supports G.823 and G.824 for 2048 kbps and 1544 kbps interfaces
Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
Simple hardware control interface
Accepts two input references and synchronizes to any combination of 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz inputs
Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
Provides 5 styles of 8 kHz framing pulses
Holdover frequency accuracy of 1 x 10-8
Lock, Holdover and Out of Range indication
Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
Less than 0.5 nspp jitter on all output clocks
External master clock source: clock oscillator or crystal

简介

ZL30101属于集成电路（IC）的应用特定时钟/定时。由制造生产的ZL30101应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。