ZL30109数据手册集成电路（IC）的应用特定时钟/定时规格书PDF

描述 Description

The ZL30109 DS1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk DS1 and E1 transmission equipment. The 19.44 MHz output makes the ZL30109 also suitable for SDH line card applications.

特性 Features

Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E
Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces
Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
Simple hardware control interface
Accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz, 19.44 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse
Holdover frequency accuracy of 1.5 x 10-7
Lock, Holdover and selectable Out of Range indication
Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with OC-3 and STM-1 jitter specifications
Less than 0.6 nspp intrinsic jitter on all output clocks
External master clock source: clock oscillator or crystal

简介

ZL30109属于集成电路（IC）的应用特定时钟/定时。由制造生产的ZL30109应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。