ZL30106数据手册集成电路（IC）的应用特定时钟/定时规格书PDF

描述 Description

The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment.The ZL30100 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.The ZL30100 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.

特性 Features

Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs
Supports output wander and jitter generation specifications for SONET/SDH and PDH interfaces
Accepts three input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
Provides automatic entry into Holdover and return from Holdover
Manual and automatic hitless reference switching Provides lock, holdover and accurate reference fail indication
Selectable loop filter bandwidth of 29 Hz or 922 Hz
Provides a range of clock outputs:2.048 MHz (E1), 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
19.44 MHz (SONET/SDH)* 1.544 MHz (DS1) and 3.088 MHz
a choice of 6.312 MHz (DS2), 8.448 MHz (E2), 44.736 MHz (DS3) or 34.368 MHz (E3)Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse

简介

ZL30106属于集成电路（IC）的应用特定时钟/定时。由制造生产的ZL30106应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。