ZL30107中文资料PDH/SDH System Synchronizer数据手册Microchip规格书

描述 Description

The ZL30107 provides timing and synchronization for Ethernet line cards in next-generation networking equipment supporting circuit services over IP-based architectures. Integrating independent analog and digital PLLs, the device synchronizes with standard telecom and Ethernet clocks and generates an IEEE 802.3 jitter compliant 25 MHz Gigabit Ethernet output clock. Backed by Microchip's leading timing and synchronization expertise, no competing device can match the performance and level of integration at the price point supported by the ZL30107 device.

特性 Features

Single chip low cost solution for synchronizing an Ethernet PHY to a standard telecom clock
Generates an IEEE 802.3 jitter compliant 25 MHz Gigabit Ethernet output clock
Supports three modes of operation: Asynchronous Freerun, Synchronous, and Asynchronous Holdover
In Asynchronous Freerun mode, the DPLL generates an output clock with a frequency accuracy equal to frequency accuracy of the external crystal oscillator (XO) or a low cost crystal (XTAL)
In Synchronous mode, the DPLL automatically synchronizes to one of a pre-defined set of frequencies including 2 kHz, 8 kHz, 64 kHz, 1.544 MHz, 2.048 MHz, 6.48 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz, 38.88 MHz, 77.76 MHz.
Configurable to accept a 25 MHz input reference
Automatic entry into Asynchronous Holdover mode when all input references fail
Lock indicator pin
Input reference status monitors
Programmable loop bandwidth of 14 Hz, 28 Hz, or 890 Hz

简介

ZL30107属于集成电路（IC）的应用特定时钟/定时。由制造生产的ZL30107应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。