ZL30108中文资料PDH/SDH System Synchronizer数据手册Microchip规格书

描述 Description

The ZL30108 SONET/SDH network interface digital phase-locked loop (DPLL) provides timing and synchronization for SONET/SDH network interface cards.  Measuring just 5 mm (millimeters) x 5 mm, the ZL30108 DPLL addresses dense line card \"real estate\" constraints. The device may be used in combination with Microchip's family of analog PLLs to provide an end-to-end timing and synchronization solution for higher-speed SONET/SDH networking equipment. For example, the ZL30108 DPLL and ZL30415 analog PLL provide an easy-to-implement, compact solution for OC-12/STM-4 line cards.

特性 Features

Supports output wander and jitter generation specifications for GR-253-CORE OC-3 and G.813 STM-1 SONET/SDH interfaces
Accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
Provides a 19.44 MHz (SONET/SDH) clock output
Provides an 8 kHz framing pulse and a 2 kHz multi-frame pulse
Provides automatic entry into Holdover and return from Holdover
Hitless reference switching
Provides lock and accurate reference fail indication
Loop filter bandwidth of 29 Hz or 14 Hz
Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications
Ultra Compact (5 mm x 5 mm) 32-pin QFN package

简介

ZL30108属于集成电路（IC）的应用特定时钟/定时。由制造生产的ZL30108应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。