ZL30111数据手册集成电路（IC）的应用特定时钟/定时规格书PDF

描述 Description

The ZL30111 POTS line card PLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices.The ZL30111 generates TDM clock and framing signals that are phase locked to the input reference. It helps ensure system reliability by monitoring its reference for stability and by maintaining stable output clocks during short periods when the reference is unavailable.

特性 Features

Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input
Provides a range of clock outputs: 2.048 MHz, 4.096 MHz and 8.192 MHz
Provides 2 styles of 8 kHz framing pulses
Automatic entry and exit from freerun mode on reference fail Provides DPLL lock and reference fail indication
DPLL bandwidth of 922 Hz for all rates of input reference and 58 Hz for an 8 kHz input reference
Less than 0.6 nsppintrinsic jitter on all output clocks
20 MHz external master clock source: clock oscillator or crystal
Simple hardware control interface

简介

ZL30111属于集成电路（IC）的应用特定时钟/定时。由制造生产的ZL30111应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。