ZL30110中文资料PDH/SDH System Synchronizer数据手册Microchip规格书

描述 Description

The ZL30110 clock rate conversion digital phase-locked loop (DPLL) provides accurate and reliable frequency conversion. The ZL30110 generates a range of clocks that are either locked to the input reference or locked to the external crystal or oscillator. In the locked mode, the reference input is continuously monitored for a failure condition. In the event of a failure, the DPLL continues to provide a stable free running clock ensuring system reliability.

特性 Features

Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz
Provides DPLL lock and reference fail indication
Automatic free run mode on reference fail
DPLL bandwidth of 922 Hz for all rates of input reference and 58 Hz for an 8 kHz input reference
Less than 5 psecrmson 25 MHz outputs, and less than 0.6 nsppintrinsic jitter on the all other outputs
Minimal input to output and output to output skew
25 MHz external master clock source: clock oscillator or crystal
Simple hardware control interface
Provides a range of output clocks:65.536 MHz TDM clock locked to the input reference
General purpose 25 MHz fan-out to 6 outputs locked to the external crystal or oscillator
General purpose 125 MHz and 66 MHz or 100 MHz locked to the external crystal or oscillator

简介

ZL30110属于集成电路（IC）的应用特定时钟/定时。由制造生产的ZL30110应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。