ZL30116中文资料SONET/SDH OC-48/OC-192 System Synchronizer数据手册Microchip规格书

描述 Description

The ZL30116 SONET/SDH System Synchronizer is a highly integrated device that provides the functionality required for synchronizing network equipment. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses.

特性 Features

• Supports the requirements of Telcordia GR-253 and GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and the requirements of ITU-T G.781 SETS, G.813 SEC, G.823, G.824 and G.825 clocks
• Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64
• Programmable output synthesizers generate clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz
• Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz
• Supports master/slave configuration for AdvancedTCATM
• Configurable input to output delay and output to output phase alignment
• Optional external feedback path provides dynamic input to output delay compensation

简介

ZL30116属于集成电路（IC）的应用特定时钟/定时。由制造生产的ZL30116应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。