ZL30112中文资料T1/E1 System Synchronizer数据手册Microchip规格书

描述 Description

The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment.The ZL30100 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.The ZL30100 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.

特性 Features

Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input
Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse
Automatic entry and exit from freerun mode on reference fail
Provides DPLL lock and reference fail indication
DPLL bandwidth of 29 Hz for all rates of input references
Less than 0.6 nsecpp intrinsic jitter on all output clocks
20 MHz external master clock source: clock oscillator or crystal
Simple hardware control interface

简介

ZL30112属于集成电路（IC）的应用特定时钟/定时。由制造生产的ZL30112应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。