3-BIT 4:1 MULTIPLEXER

DESCRIPTION The SY10/100E171 offer three 4:1 multiplexers with differential outputs, designed for use in new, highperformance ECL systems. The leading 4-bit multiplexer operation is organized pairwise, with each pair being a 2- bit multiplexer. FEATURES ■ 725ps max. D to output ■ Extended 100E

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3-BIT 4:1 MULTIPLEXER

DESCRIPTION The SY10/100E171 offer three 4:1 multiplexers with differential outputs, designed for use in new, highperformance ECL systems. The leading 4-bit multiplexer operation is organized pairwise, with each pair being a 2- bit multiplexer. FEATURES ■ 725ps max. D to output ■ Extended 100E

文件：60.29 Kbytes 页数：4 Pages

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3-BIT 4:1 MULTIPLEXER

DESCRIPTION The SY10/100E171 offer three 4:1 multiplexers with differential outputs, designed for use in new, highperformance ECL systems. The leading 4-bit multiplexer operation is organized pairwise, with each pair being a 2- bit multiplexer. FEATURES ■ 725ps max. D to output ■ Extended 100E

文件：60.29 Kbytes 页数：4 Pages

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9-BIT LATCH WITH PARITY

DESCRIPTION The SY10/100E175 are 9-bit latches. They also feature a tenth latched output (ODDPAR) which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type s

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9-BIT LATCH WITH PARITY

DESCRIPTION The SY10/100E175 are 9-bit latches. They also feature a tenth latched output (ODDPAR) which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type s

文件：60.34 Kbytes 页数：4 Pages

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9-BIT LATCH WITH PARITY

DESCRIPTION The SY10/100E175 are 9-bit latches. They also feature a tenth latched output (ODDPAR) which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type s

文件：60.34 Kbytes 页数：4 Pages

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ERROR DETECTION/ CORRECTION CIRCUIT

DESCRIPTION The SY10/100E193 are error detection and correction (EDAC) circuits designed for use in new, high- performance ECL systems. The E193 generates hamming parity codes on an 8-bit word as shown in the block diagram. The P5 output gives the parity of the whole word. PGEN provides word pari

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ERROR DETECTION/ CORRECTION CIRCUIT

DESCRIPTION The SY10/100E193 are error detection and correction (EDAC) circuits designed for use in new, high- performance ECL systems. The E193 generates hamming parity codes on an 8-bit word as shown in the block diagram. The P5 output gives the parity of the whole word. PGEN provides word pari

文件：62.81 Kbytes 页数：4 Pages

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ERROR DETECTION/ CORRECTION CIRCUIT

DESCRIPTION The SY10/100E193 are error detection and correction (EDAC) circuits designed for use in new, high- performance ECL systems. The E193 generates hamming parity codes on an 8-bit word as shown in the block diagram. The P5 output gives the parity of the whole word. PGEN provides word pari

文件：62.81 Kbytes 页数：4 Pages

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PROGRAMMABLE DELAY CHIP

DESCRIPTION The SY10/100E195 are programmable delay chips (PDCs) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in the logic diagram. The first tw

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