12-BIT PARITY GENERATOR/CHECKER

DESCRIPTION The SY10/100E160 are high-speed, 12-bit parity generator/checkers with differential outputs, for use in new, high-performance ECL systems. The output Q takes on a logic HIGH value only when an odd number of inputs are at a logic HIGH. A logic HIGH on the enable input (EN) forces the o

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12-BIT PARITY GENERATOR/CHECKER

DESCRIPTION The SY10/100E160 are high-speed, 12-bit parity generator/checkers with differential outputs, for use in new, high-performance ECL systems. The output Q takes on a logic HIGH value only when an odd number of inputs are at a logic HIGH. A logic HIGH on the enable input (EN) forces the o

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2-BIT 8:1 MULTIPLEXER

DESCRIPTION The SY10/100E163 offer two 8:1 multiplexers designed for use in new, high-performance ECL systems. The E163 has differential outputs and common select inputs. The select inputs (SEL0, SEL1, SEL2) determine which one o the eight data inputs (A0–A7, B0–B7) is propagated to the output.

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2-BIT 8:1 MULTIPLEXER

DESCRIPTION The SY10/100E163 offer two 8:1 multiplexers designed for use in new, high-performance ECL systems. The E163 has differential outputs and common select inputs. The select inputs (SEL0, SEL1, SEL2) determine which one o the eight data inputs (A0–A7, B0–B7) is propagated to the output.

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16:1 MULTIPLEXER

DESCRIPTION The SY10/100E164 are 16:1 multiplexers with a differential output. The select inputs (SEL0,1,2,3) control which one of the sixteen data inputs (A0–A15) is propagated to the output. Special attention to the design layout results in a typical skew between the 16 inputs of only 50ps. F

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16:1 MULTIPLEXER

DESCRIPTION The SY10/100E164 are 16:1 multiplexers with a differential output. The select inputs (SEL0,1,2,3) control which one of the sixteen data inputs (A0–A15) is propagated to the output. Special attention to the design layout results in a typical skew between the 16 inputs of only 50ps. F

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9-BIT MAGNITUDE COMPARATOR

DESCRIPTION The SY10/100E166 are 9-bit magnitude comparators designed for use in new, high-performance ECL systems. The E166 compares the binary value of two 9-bit words and indicates whether one word is greater than or equal to the other. FEATURES ■ 1100ps max. Propagation Delay A = B ■ Exten

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9-BIT MAGNITUDE COMPARATOR

DESCRIPTION The SY10/100E166 are 9-bit magnitude comparators designed for use in new, high-performance ECL systems. The E166 compares the binary value of two 9-bit words and indicates whether one word is greater than or equal to the other. FEATURES ■ 1100ps max. Propagation Delay A = B ■ Exten

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6-BIT 2:1 MUX-REGISTER

DESCRIPTION The SY10/100E167 offer six 2:1 multiplexers followed by D flip-flops with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 1000MHz min. operating frequency ■ Extended 100E VEE range of –4.2V to –5.5V ■ 800ps max. clock to output ■ Single-en

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6-BIT 2:1 MUX-REGISTER

DESCRIPTION The SY10/100E167 offer six 2:1 multiplexers followed by D flip-flops with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 1000MHz min. operating frequency ■ Extended 100E VEE range of –4.2V to –5.5V ■ 800ps max. clock to output ■ Single-en

文件：155.24 Kbytes 页数：3 Pages

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