6-BIT D LATCH

DESCRIPTION The SY10/100E150 are 6-bit D latches with differential outputs designed for use in new, high- performance ECL systems. When both Latch Enables (LEN1, LEN2) are at a logic LOW, the latch is in the transparent mode and input data propagates through to the output. A logic HIGH on either

文件：60.6 Kbytes 页数：4 Pages

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麦瑞半导体

6-BIT D REGISTER

DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for

文件：66.31 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

6-BIT D REGISTER

DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for

文件：66.31 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

6-BIT D REGISTER

DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for

文件：66.31 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

6-BIT D REGISTER

DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for

文件：66.31 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

5-BIT 2:1 MUX-LATCH

DESCRIPTION The SY10/100E154 offer five 2:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external Latch-Enable signals (LEN1, LEN2) are gated through a logical OR operation before use as control for the five latches. Wh

文件：61.36 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

5-BIT 2:1 MUX-LATCH

DESCRIPTION The SY10/100E154 offer five 2:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external Latch-Enable signals (LEN1, LEN2) are gated through a logical OR operation before use as control for the five latches. Wh

文件：61.36 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

6-BIT 2:1 MUX-LATCH

DESCRIPTION The SY10/100E155 offer six 2:1 multiplexers followed by latches with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 750ps max. LEN to output ■ Extended 100E VEE range of –4.2V to –5.5V ■ 700ps max. D to output ■ Single-ended outputs ■ As

文件：60.59 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

6-BIT 2:1 MUX-LATCH

DESCRIPTION The SY10/100E155 offer six 2:1 multiplexers followed by latches with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 750ps max. LEN to output ■ Extended 100E VEE range of –4.2V to –5.5V ■ 700ps max. D to output ■ Single-ended outputs ■ As

文件：60.59 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

6-BIT 2:1 MUX-LATCH

DESCRIPTION The SY10/100E155 offer six 2:1 multiplexers followed by latches with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 750ps max. LEN to output ■ Extended 100E VEE range of –4.2V to –5.5V ■ 700ps max. D to output ■ Single-ended outputs ■ As

文件：60.59 Kbytes 页数：4 Pages

MICREL

麦瑞半导体