PROGRAMMABLE DELAY CHIP

DESCRIPTION The SY10/100E195 are programmable delay chips (PDCs) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in the logic diagram. The first tw

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PROGRAMMABLE DELAY CHIP

DESCRIPTION The SY10/100E195 are programmable delay chips (PDCs) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in the logic diagram. The first tw

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PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT

DESCRIPTION The SY10/100E196 are programmable delay chips (PDCs) designed primarily for very accurate differential ECL input edge placement applications FEATURES ■ Up to 2ns delay range ■ Extended 100E VEE range of –4.2V to –5.5V ■ ≈20ps digital step resolution ■ Linear input for tighter res

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PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT

DESCRIPTION The SY10/100E196 are programmable delay chips (PDCs) designed primarily for very accurate differential ECL input edge placement applications FEATURES ■ Up to 2ns delay range ■ Extended 100E VEE range of –4.2V to –5.5V ■ ≈20ps digital step resolution ■ Linear input for tighter res

文件：79.64 Kbytes 页数：9 Pages

MICREL

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PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT

DESCRIPTION The SY10/100E196 are programmable delay chips (PDCs) designed primarily for very accurate differential ECL input edge placement applications FEATURES ■ Up to 2ns delay range ■ Extended 100E VEE range of –4.2V to –5.5V ■ ≈20ps digital step resolution ■ Linear input for tighter res

文件：79.64 Kbytes 页数：9 Pages

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3-BIT SCANNABLE REGISTER

DESCRIPTION The SY10/100E212 are scannable registered ECL drivers typically used as fan-out memory address drivers for ECL cache driving. In a VLSI array-based CPU design, use of the E212 allows the user to conserve array output cell functionality and also output pins. The input shift register i

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3-BIT SCANNABLE REGISTER

DESCRIPTION The SY10/100E212 are scannable registered ECL drivers typically used as fan-out memory address drivers for ECL cache driving. In a VLSI array-based CPU design, use of the E212 allows the user to conserve array output cell functionality and also output pins. The input shift register i

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8-BIT SCANNABLE REGISTER

DESCRIPTION The SY10/100E241 are 8-bit shiftable registers designed for use in new, high-performance ECL systems. Unlike the E141, the E241 features internal data feedback organized such that the SHIFT control overrides the HOLD, /LOAD control. Thus, the normal operations of HOLD and LOAD can be

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8-BIT SCANNABLE REGISTER

DESCRIPTION The SY10/100E241 are 8-bit shiftable registers designed for use in new, high-performance ECL systems. Unlike the E141, the E241 features internal data feedback organized such that the SHIFT control overrides the HOLD, /LOAD control. Thus, the normal operations of HOLD and LOAD can be

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3-BIT 4:1 MUX-LATCH

DESCRIPTION The SY10/100E256 offer three 4:1 multiplexers followed by latches with differential outputs designed for use in new, high-performance ECL systems. Separate Select controls are provided for the leading 2:1 mux pairs (see block diagram). FEATURES ■ 950ps max. data to output ■ Extende

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