SY100E195JC技术资料参数贸易商麦瑞半导体-114ic电子网

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型号	下载订购	功能描述	制造商上传企业	LOGO
SY100E195JC	文件：75.45 Kbytes Page：8 Pages	PROGRAMMABLE DELAY CHIP DESCRIPTION The SY10/100E195 are programmable delay chips (PDCs) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in the logic diagram. The first tw 文件：75.45 Kbytes 页数：8 Pages	Micrel 麦瑞半导体	Micrel
SY100E195JCTR	文件：75.45 Kbytes Page：8 Pages	PROGRAMMABLE DELAY CHIP DESCRIPTION The SY10/100E195 are programmable delay chips (PDCs) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in the logic diagram. The first tw 文件：75.45 Kbytes 页数：8 Pages	Micrel 麦瑞半导体	Micrel
SY100E195JI	文件：77.62 Kbytes Page：8 Pages	PROGRAMMABLE DELAY CHIP 文件：77.62 Kbytes 页数：8 Pages	Micrel 麦瑞半导体	Micrel
SY100E195JITR	文件：77.62 Kbytes Page：8 Pages	PROGRAMMABLE DELAY CHIP 文件：77.62 Kbytes 页数：8 Pages	Micrel 麦瑞半导体	Micrel
SY100E195JY	文件：77.62 Kbytes Page：8 Pages	PROGRAMMABLE DELAY CHIP 文件：77.62 Kbytes 页数：8 Pages	Micrel 麦瑞半导体	Micrel

更多SY100E195JC供应商更新时间2025-11-30 10:18:00