4-BIT PARALLEL-TO-SERIAL CONVERTER

DESCRIPTION The SY10/100E446 are integrated 4-bit parallel-to-serial data converters. These devices are designed to operate for NRZ data rates of up to a minimum of 1.3Gb/s. The chips generate a divide-by-4 and a divide-by-8 clock for both 4-bit conversion and a two-chip 8-bit conversion function

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4-BIT PARALLEL-TO-SERIAL CONVERTER

DESCRIPTION The SY10/100E446 are integrated 4-bit parallel-to-serial data converters. These devices are designed to operate for NRZ data rates of up to a minimum of 1.3Gb/s. The chips generate a divide-by-4 and a divide-by-8 clock for both 4-bit conversion and a two-chip 8-bit conversion function

文件：85.02 Kbytes 页数：9 Pages

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6-BIT REGISTER DIFFERENTIAL DATA CLOCK

DESCRIPTION The SY10/100E451 offer six D-type flip-flops with single-ended outputs and differential data and clock inputs, designed for use in new, high-performance ECL systems. The registers are triggered by the rising edge of the CLK input. FEATURES ■ 1100MHz min. toggle frequency ■ Extended

文件：63.13 Kbytes 页数：4 Pages

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6-BIT REGISTER DIFFERENTIAL DATA CLOCK

DESCRIPTION The SY10/100E451 offer six D-type flip-flops with single-ended outputs and differential data and clock inputs, designed for use in new, high-performance ECL systems. The registers are triggered by the rising edge of the CLK input. FEATURES ■ 1100MHz min. toggle frequency ■ Extended

文件：63.13 Kbytes 页数：4 Pages

MICREL

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5-BIT DIFFERENTIAL REGISTER

DESCRIPTION The SY10/100E452 are 5-bit differential registers with differential data (inputs and outputs) and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A high on the Master Reset (MR) asynchronously resets all registers so that the Q outputs go

文件：63.08 Kbytes 页数：4 Pages

MICREL

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5-BIT DIFFERENTIAL REGISTER

DESCRIPTION The SY10/100E452 are 5-bit differential registers with differential data (inputs and outputs) and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A high on the Master Reset (MR) asynchronously resets all registers so that the Q outputs go

文件：63.08 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

5-BIT DIFFERENTIAL REGISTER

DESCRIPTION The SY10/100E452 are 5-bit differential registers with differential data (inputs and outputs) and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A high on the Master Reset (MR) asynchronously resets all registers so that the Q outputs go

文件：63.08 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

5-BIT DIFFERENTIAL REGISTER

DESCRIPTION The SY10/100E452 are 5-bit differential registers with differential data (inputs and outputs) and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A high on the Master Reset (MR) asynchronously resets all registers so that the Q outputs go

文件：63.08 Kbytes 页数：4 Pages

MICREL

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TRIPLE DIFFERENTIAL 2:1 MULTIPLEXER

DESCRIPTION The SY10/100E457 are 3-bit differential 2:1 multiplexers. The fully differential data path makes the devices ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided to ease AC coupling input signals. FEATURES ■ Differential D and Q ■ Ex

文件：61.27 Kbytes 页数：4 Pages

MICREL

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TRIPLE DIFFERENTIAL 2:1 MULTIPLEXER

DESCRIPTION The SY10/100E457 are 3-bit differential 2:1 multiplexers. The fully differential data path makes the devices ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided to ease AC coupling input signals. FEATURES ■ Differential D and Q ■ Ex

文件：61.27 Kbytes 页数：4 Pages

MICREL

麦瑞半导体