3-BIT 4:1 MUX-LATCH

DESCRIPTION The SY10/100E256 offer three 4:1 multiplexers followed by latches with differential outputs designed for use in new, high-performance ECL systems. Separate Select controls are provided for the leading 2:1 mux pairs (see block diagram). FEATURES ■ 950ps max. data to output ■ Extende

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3-BIT REGISTERED BUS TRANSCEIVER

DESCRIPTION The SY10/100E336 offer three bus transceivers with both transmit and receive registers and are designed for use in new, high-performance ECL systems. The bus outputs (BUS0 - BUS2) are designed to drive a 25Ω bus. The receive outputs (Q0 – Q2) are specified for 50Ω. The bus outputs fea

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3-BIT REGISTERED BUS TRANSCEIVER

DESCRIPTION The SY10/100E336 offer three bus transceivers with both transmit and receive registers and are designed for use in new, high-performance ECL systems. The bus outputs (BUS0 - BUS2) are designed to drive a 25Ω bus. The receive outputs (Q0 – Q2) are specified for 50Ω. The bus outputs fea

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3-BIT SCANNABLE

DESCRIPTION The SY10/100E337 are 3-bit registered bus transceivers with scan designed for use in new, high- performance ECL systems. The bus outputs (BUS0–BUS2) are designed to drive a 25Ω bus; the receive outputs (Q0–Q2) are designed for 50Ω. The bus outputs feature a normal logic HIGH level (VO

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3-BIT SCANNABLE

DESCRIPTION The SY10/100E337 are 3-bit registered bus transceivers with scan designed for use in new, high- performance ECL systems. The bus outputs (BUS0–BUS2) are designed to drive a 25Ω bus; the receive outputs (Q0–Q2) are designed for 50Ω. The bus outputs feature a normal logic HIGH level (VO

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QUAD DIFFERENTIAL AND/NAND

DESCRIPTION The SY10/100E404 are 4-bit differential AND/NAND devices. The differential operation of these devices make them ideal for pulse shaping applications where duty cycle skew is critical. Special design techniques were incorporated to minimize the skew between the upper and lower level ga

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QUAD DIFFERENTIAL AND/NAND

DESCRIPTION The SY10/100E404 are 4-bit differential AND/NAND devices. The differential operation of these devices make them ideal for pulse shaping applications where duty cycle skew is critical. Special design techniques were incorporated to minimize the skew between the upper and lower level ga

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QUINT DIFFERENTIAL LINE RECEIVER

DESCRIPTION The SY10/100E416 are 5-bit differential line receiving devices. The 2.0GHz of bandwidth provided by the high frequency outputs make the devices ideal for buffering of very high speed oscillators. A VBB pin is available to AC couple an input signal to the devices. The design incorpor

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QUINT DIFFERENTIAL LINE RECEIVER

DESCRIPTION The SY10/100E416 are 5-bit differential line receiving devices. The 2.0GHz of bandwidth provided by the high frequency outputs make the devices ideal for buffering of very high speed oscillators. A VBB pin is available to AC couple an input signal to the devices. The design incorpor

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QUINT LVPECL-TO-PECL OR PECL-TO-LVPECL TRANSLATOR

DESCRIPTION The SY100E417 is a quint LVPECL-to-PECL translator. It can also be used as a quint PECL-to-LVPECL translator. The device receives standard PECL signals and translates them to differential LVPECL output signals (or vice versa). The SY100E417 can also be used as a differential line rec

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