SY100E337JCTR中文资料麦瑞半导体数据手册PDF规格书

DESCRIPTION

The SY10/100E337 are 3-bit registered bus transceivers with scan designed for use in new, high- performance ECL systems. The bus outputs (BUS0–BUS2) are designed to drive a 25Ω bus; the receive outputs (Q0–Q2) are designed for 50Ω. The bus outputs feature a normal logic HIGH level (VOH) and a cutoff LOW level of –2.0V and the output emitter-follower is “off”, presenting a high impedance to the bus. The bus outputs also feature edge slow-down capacitors.

FEATURES

■ 1500ps max. clock to bus (data transmit)

■ 1000ps max. clock to Q (data receive)

■ Extended 100E VEE range of –4.2V to –5.5V

■ 25Ω cutoff bus outputs

■ 50Ω receiver outputs

■ Scannable implementation of E336

■ Synchronous and asynchronous bus enables

■ Non-inverting data path

■ Bus outputs feature internal edge slow-down capacitors

■ Additional package ground pins

■ Fully compatible with industry standard 10KH, 100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E337

■ Available in 28-pin PLCC package