3-BIT 4:1 MUX-LATCH

DESCRIPTION The SY10/100E156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external latch enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the three latche

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3-BIT 4:1 MUX-LATCH

DESCRIPTION The SY10/100E156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external latch enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the three latche

文件：60.87 Kbytes 页数：4 Pages

MICREL

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3-BIT 4:1 MUX-LATCH

DESCRIPTION The SY10/100E156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external latch enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the three latche

文件：60.87 Kbytes 页数：4 Pages

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QUAD 2:1 MULTIPLEXER

DESCRIPTION The SY10/100E157 contain four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs. FEATURES ■ Individual select controls ■ Extended 100

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QUAD 2:1 MULTIPLEXER

DESCRIPTION The SY10/100E157 contain four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs. FEATURES ■ Individual select controls ■ Extended 100

文件：59 Kbytes 页数：4 Pages

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QUAD 2:1 MULTIPLEXER

DESCRIPTION The SY10/100E157 contain four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs. FEATURES ■ Individual select controls ■ Extended 100

文件：59 Kbytes 页数：4 Pages

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5-BIT 2:1 MULTIPLEXER

DESCRIPTION The SY10/100E158 offer five 2:1 multiplexers with differential outputs, designed for use in new, high performance ECL systems. The multiplexer operation is controlled by the SEL (Select) signal which selects one of the two bits of input data at each mux to be passed through. FEATURE

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5-BIT 2:1 MULTIPLEXER

DESCRIPTION The SY10/100E158 offer five 2:1 multiplexers with differential outputs, designed for use in new, high performance ECL systems. The multiplexer operation is controlled by the SEL (Select) signal which selects one of the two bits of input data at each mux to be passed through. FEATURE

文件：58.23 Kbytes 页数：4 Pages

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5-BIT 2:1 MULTIPLEXER

DESCRIPTION The SY10/100E158 offer five 2:1 multiplexers with differential outputs, designed for use in new, high performance ECL systems. The multiplexer operation is controlled by the SEL (Select) signal which selects one of the two bits of input data at each mux to be passed through. FEATURE

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12-BIT PARITY GENERATOR/CHECKER

DESCRIPTION The SY10/100E160 are high-speed, 12-bit parity generator/checkers with differential outputs, for use in new, high-performance ECL systems. The output Q takes on a logic HIGH value only when an odd number of inputs are at a logic HIGH. A logic HIGH on the enable input (EN) forces the o

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