6-BIT D REGISTER

DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for

文件：66.31 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

6-BIT D REGISTER

文件：63.16 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

6-BIT D REGISTER

文件：64.129 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

6-BIT D REGISTER

DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for

文件：66.31 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

6-BIT D REGISTER

DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for

文件：66.31 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

6-BIT D REGISTER

文件：63.16 Kbytes 页数：4 Pages

MICREL

麦瑞半导体