SY100E160JCTR中文资料麦瑞半导体数据手册PDF规格书

DESCRIPTION

The SY10/100E160 are high-speed, 12-bit parity generator/checkers with differential outputs, for use in new, high-performance ECL systems. The output Q takes on a logic HIGH value only when an odd number of inputs are at a logic HIGH. A logic HIGH on the enable input (EN) forces the output Q to a logic LOW.

FEATURES

■ Provides odd-HIGH parity of 12 inputs

■ Extended 100E VEE range of –4.2V to –5.5V

■ Output register with Shift/Hold capability

■ 900ps max. D to Q, /Q output

■ Enable control

■ Asynchronous Register Reset

■ Differential outputs

■ Fully compatible with industry standard 10KH, 100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E160

■ Available in 28-pin PLCC package