SY100E193JCTR中文资料麦瑞半导体数据手册PDF规格书

DESCRIPTION

The SY10/100E193 are error detection and correction (EDAC) circuits designed for use in new, high- performance ECL systems. The E193 generates hamming parity codes on an 8-bit word as shown in the block diagram. The P5 output gives the parity of the whole word. PGEN provides word parity after Odd/Even parity control and gating with the BPAR input. PGEN also feeds into a 1-bit shiftable register for use as part of a scan ring.

FEATURES

■ Hamming code generation

■ Extended 100E VEE range of –4.2V to –5.5V

■ 8-bit wide

■ Expandable for more width

■ Provides parity register

■ Fully compatible with industry standard 10KH, 100K ECL levels

■ Internal75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E193

■ Available in 28-pin PLCC package