DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS

[PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02

文件：208.36 Kbytes 页数：7 Pages

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DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS

DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn

文件：147.6 Kbytes 页数：7 Pages

PLL

DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS

DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and

文件：149.35 Kbytes 页数：7 Pages

PLL

DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS

DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and

文件：149.35 Kbytes 页数：7 Pages

PLL

DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS

DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and

文件：149.35 Kbytes 页数：7 Pages

PLL

DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS

DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and

文件：149.35 Kbytes 页数：7 Pages

PLL

1-to-4 Clock Distribution Buffer

DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out

文件：122.59 Kbytes 页数：4 Pages

PLL

1-to-4 Clock Distribution Buffer

DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out

文件：122.59 Kbytes 页数：4 Pages

PLL

1-to-4 Clock Distribution Buffer

DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out

文件：122.59 Kbytes 页数：4 Pages

PLL

1-to-4 Clock Distribution Buffer

DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out

文件：122.59 Kbytes 页数：4 Pages

PLL