PLL103-04中文资料PLL数据手册PDF规格书

DESCRIPTIONS

The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all outputs.

FEATURES

• 4 outputs identical to FIN.

• Low skew (< 250 ps between outputs).

• Input / Output frequency range 0 – 160 MHz

• 25mA drive capability at TTL levels.

• 70mA drive capability at CMOS levels.

• Output enable mode available to tri-state all outputs.

• 3.3V operation.

• Available in 8-Pin 150mil SOIC.