PLL103-02中文资料etc未分类制造商数据手册PDF规格书

[PLL]

DESCRIPTIONS

The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 266 chipset. The PLL103-02 also has an I2C interface, which can enable or disable each output clock. When power up, all output clocks are enabled (has internal pull up).

FEATURES

• Generates 24 output buffer from one input.

• Supports up to four DDR DIMMS or 2 SDRAM DIMMS.

• Supports 266MHz DDR SDRAM.

• One additional output for feedback.

• Less than 5ns delay.

• Skew between any outputs is less than 100 ps.

• 2.5V or 3.3V Supply range.

• Enhanced DDR and SDRAM Output Drive selected by I2C.

• Available in 48 pin SSOP.