PLL102-15SC中文资料PLL数据手册PDF规格书

DESCRIPTIONS

The PLL102-15 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8 -pin SOIC or TSSOP package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feedback to the input of the PLL. Since the skew b etween the input and output is less than ±350 ps, the device acts as a zero delay buffer.

FEATURES

• Frequency range 25 ~ 60MHz.

• Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation).

• Zero input - output delay.

• Less than 700 ps device - device skew.

• Less than 250 ps skew between outputs.

• Less than 200 ps cycle - cycle jitter.

• Output Enable function tri-state outputs.

• 3.3V operation.

• Available in 8 -Pin 150mil SOIC.