1-to-5 Clock Distribution Buffer

DESCRIPTIONS The PLL103-05 is a 1-to-5 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 5 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. FEATURES • 5 outputs identical to FIN. • Low skew (

文件：122.15 Kbytes 页数：4 Pages

PLL

1-to-5 Clock Distribution Buffer

DESCRIPTIONS The PLL103-05 is a 1-to-5 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 5 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. FEATURES • 5 outputs identical to FIN. • Low skew (

文件：122.15 Kbytes 页数：4 Pages

PLL

1-to-5 Clock Distribution Buffer

DESCRIPTIONS The PLL103-05 is a 1-to-5 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 5 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. FEATURES • 5 outputs identical to FIN. • Low skew (

文件：122.15 Kbytes 页数：4 Pages

PLL

1-to-5 Clock Distribution Buffer

DESCRIPTIONS The PLL103-05 is a 1-to-5 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 5 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. FEATURES • 5 outputs identical to FIN. • Low skew (

文件：122.15 Kbytes 页数：4 Pages

PLL

DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS

DESCRIPTIONS The PLL103-06 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-06 can be used in conjunction with

文件：145.87 Kbytes 页数：7 Pages

PLL

DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS

DESCRIPTIONS The PLL103-06 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-06 can be used in conjunction with

文件：145.87 Kbytes 页数：7 Pages

PLL

DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS

DESCRIPTIONS The PLL103-06 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-06 can be used in conjunction with

文件：145.87 Kbytes 页数：7 Pages

PLL

DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS

DESCRIPTIONS The PLL103-06 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-06 can be used in conjunction with

文件：145.87 Kbytes 页数：7 Pages

PLL

2 DIMM DDR Fanout Buffer

DESCRIPTIONS The PLL103-07 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 2 DDR DIMMs. The PLL103-07 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 2

文件：144.26 Kbytes 页数：7 Pages

PLL

2 DIMM DDR Fanout Buffer

DESCRIPTIONS The PLL103-07 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 2 DDR DIMMs. The PLL103-07 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 2

文件：144.26 Kbytes 页数：7 Pages

PLL