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[Z-Communications, Inc.] FEATURES • Frequency Range: 1055 - 1105 MHz • Step Size: 30 KHz • PLL - Style Package APPLICATIONS • Basestations • Mobile Radios • Satellite Communications

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High Speed Translator Buffer to PECL (Enable Low)

DESCRIPTION The PLL130-05 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.3GHz. It provides one pair of differential PECL outputs. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for conversion fro

文件：208.66 Kbytes 页数：4 Pages

PLL

High Speed Translator Buffer to PECL (Enable Low)

DESCRIPTION The PLL130-05 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.3GHz. It provides one pair of differential PECL outputs. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for conversion fro

文件：208.66 Kbytes 页数：4 Pages

PLL

High Speed Translator Buffer to PECL (Enable Low)

DESCRIPTION The PLL130-05 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.3GHz. It provides one pair of differential PECL outputs. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for conversion fro

文件：208.66 Kbytes 页数：4 Pages

PLL

High Speed Translator Buffer to PECL (Enable Low)

DESCRIPTION The PLL130-05 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.3GHz. It provides one pair of differential PECL outputs. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for conversion fro

文件：208.66 Kbytes 页数：4 Pages

PLL

High Speed Translator Buffer to PECL (Enable Low)

DESCRIPTION The PLL130-05 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.3GHz. It provides one pair of differential PECL outputs. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for conversion fro

文件：208.66 Kbytes 页数：4 Pages

PLL

High Speed Translator Buffer to PECL (Enable Low)

DESCRIPTION The PLL130-05 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.3GHz. It provides one pair of differential PECL outputs. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for conversion fro

文件：208.66 Kbytes 页数：4 Pages

PLL

High Speed Translator Buffer to CMOS (Selectable Drive)

DESCRIPTION The PLL130-07 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 200MHz. It provides CMOS output with 15pF output load drive capability. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for

文件：231.17 Kbytes 页数：5 Pages

PLL

High Speed Translator Buffer to CMOS (Selectable Drive)

DESCRIPTION The PLL130-07 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 200MHz. It provides CMOS output with 15pF output load drive capability. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for

文件：231.17 Kbytes 页数：5 Pages

PLL

High Speed Translator Buffer to CMOS (Selectable Drive)

DESCRIPTION The PLL130-07 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 200MHz. It provides CMOS output with 15pF output load drive capability. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for

文件：231.17 Kbytes 页数：5 Pages

PLL