2 DIMM DDR Fanout Buffer

DESCRIPTIONS The PLL103-07 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 2 DDR DIMMs. The PLL103-07 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 2

文件：144.26 Kbytes 页数：7 Pages

PLL

2 DIMM DDR Fanout Buffer

DESCRIPTIONS The PLL103-07 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 2 DDR DIMMs. The PLL103-07 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 2

文件：144.26 Kbytes 页数：7 Pages

PLL

Low Skew Buffers

FEATURES • Generates 13 copies of High-speed clock inputs. • Supports up to three SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin

文件：147.69 Kbytes 页数：7 Pages

PLL

Low Skew Buffers

FEATURES • Generates 13 copies of High-speed clock inputs. • Supports up to three SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin

文件：147.69 Kbytes 页数：7 Pages

PLL

Low Skew Buffers

FEATURES • Generates 13 copies of High-speed clock inputs. • Supports up to three SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin

文件：147.69 Kbytes 页数：7 Pages

PLL

Low Skew Buffers

FEATURES • Generates 13 copies of High-speed clock inputs. • Supports up to three SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin

文件：147.69 Kbytes 页数：7 Pages

PLL

DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS

DESCRIPTIONS The PLL103-53 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 30 outputs. These outputs can be configured to support 4 unbuffered DDR (Double Data Rate) DIMMS or to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 D

文件：148.62 Kbytes 页数：7 Pages

PLL

DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS

DESCRIPTIONS The PLL103-53 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 30 outputs. These outputs can be configured to support 4 unbuffered DDR (Double Data Rate) DIMMS or to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 D

文件：148.62 Kbytes 页数：7 Pages

PLL

DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS

DESCRIPTIONS The PLL103-53 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 30 outputs. These outputs can be configured to support 4 unbuffered DDR (Double Data Rate) DIMMS or to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 D

文件：148.62 Kbytes 页数：7 Pages

PLL

DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS

DESCRIPTIONS The PLL103-53 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 30 outputs. These outputs can be configured to support 4 unbuffered DDR (Double Data Rate) DIMMS or to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 D

文件：148.62 Kbytes 页数：7 Pages

PLL