DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS

DESCRIPTIONS The PLL103-53 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 30 outputs. These outputs can be configured to support 4 unbuffered DDR (Double Data Rate) DIMMS or to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 D

文件：148.62 Kbytes 页数：7 Pages

PLL

DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS

DESCRIPTIONS The PLL103-53 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 30 outputs. These outputs can be configured to support 4 unbuffered DDR (Double Data Rate) DIMMS or to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 D

文件：148.62 Kbytes 页数：7 Pages

PLL

DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS

DESCRIPTIONS The PLL103-53 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 30 outputs. These outputs can be configured to support 4 unbuffered DDR (Double Data Rate) DIMMS or to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 D

文件：148.62 Kbytes 页数：7 Pages

PLL

DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS

DESCRIPTIONS The PLL103-53 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 30 outputs. These outputs can be configured to support 4 unbuffered DDR (Double Data Rate) DIMMS or to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 D

文件：148.62 Kbytes 页数：7 Pages

PLL