1-to-4 Clock Distribution Buffer

DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out

文件：122.59 Kbytes 页数：4 Pages

PLL

1-to-4 Clock Distribution Buffer

DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out

文件：122.59 Kbytes 页数：4 Pages

PLL

1-to-4 Clock Distribution Buffer

DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out

文件：122.59 Kbytes 页数：4 Pages

PLL

LOW PROFILE THROUGH-HOLE HEADER

文件：1.3429 Mbytes 页数：1 Pages

Samtec

美国申泰