Mobile Double Data Rate (DDR) SDRAM

General Description The 256Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. On the x16 device, each of the 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. On the x32 de

文件：112.62 Kbytes 页数：3 Pages

Micron

美光

512Mb: x16, x32 Mobile Low-Power DDR SDRAM Features

Mobile Low-Power DDR SDRAM Features • VDD/VDDQ = 1.70–1.95V • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positi

文件：3.10679 Mbytes 页数：96 Pages

Micron

美光

512Mb: x16, x32 Mobile Low-Power DDR SDRAM Features

Mobile Low-Power DDR SDRAM Features • VDD/VDDQ = 1.70–1.95V • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positi

文件：3.10679 Mbytes 页数：96 Pages

Micron

美光

512Mb: x16, x32 Mobile Low-Power DDR SDRAM Features

Mobile Low-Power DDR SDRAM Features • VDD/VDDQ = 1.70–1.95V • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positi

文件：3.10679 Mbytes 页数：96 Pages

Micron

美光

512Mb: x16, x32 Mobile Low-Power DDR SDRAM Features

Mobile Low-Power DDR SDRAM Features • VDD/VDDQ = 1.70–1.95V • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positi

文件：3.10679 Mbytes 页数：96 Pages

Micron

美光

Mobile Double Data Rate (DDR) SDRAM

General Description The 256Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. On the x16 device, each of the 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. On the x32 de

文件：112.62 Kbytes 页数：3 Pages

Micron

美光

DOUBLE DATA RATE DDR SDRAM

Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce

文件：2.55598 Mbytes 页数：68 Pages

Micron

美光

512Mb: x4, x8, x16 Double Data Rate SDRAM Features

Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce

文件：1.66163 Mbytes 页数：93 Pages

Micron

美光

DOUBLE DATA RATE DDR SDRAM

Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce

文件：2.55598 Mbytes 页数：68 Pages

Micron

美光

DOUBLE DATA RATE DDR SDRAM

Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce

文件：2.55598 Mbytes 页数：68 Pages

Micron

美光